Recently, semiconductor memory devices such as a NAND flash memory employ a configuration in accordance with the miniaturization in which one control circuit, one arithmetic circuit, one data bus, and the like are shared in units of one or more cell columns. Accordingly, the circuit scale of the control circuit and the like can be deceased, whereby an increase in the chip area can be suppressed. Particularly when one control circuit and the like are shared in units of a plurality of cell columns, it is large effective to suppress the chip area.
However, for example, in a case where a plurality of sense amplifiers and data latches, one control circuit, and the like for data processing of n cell columns are configured as one unit (a sense amplifier-data latch unit or a cell column unit), a total number of cell columns of the semiconductor memory device is limited to a multiple of n.